Aim In this lab aim is the design 4- bit Arithmetic and Logic Unit (ALU) and implement the ALU on FPGA using modular design, after that, experimentally check the operation of the ALU on Spartan board Implementation Mux I designed the multiplexers. These are 2 to 1 , 4 to 1 and 2 to 1…
Tag: Logisim
4-bit Comparator on Xilinx Spartan 3A
4-bit Comparator on Xilinx Spartan 3A The aim of this experiment is to make familiar with the elementary logic gates while designing 4-bit comparator circuits for unsigned and 2’s complement systems. I will design my circuit using Xilinx ISE software as performed in the first experiment. Then I will simulate my circuit behavior and deploy…
XOR gate in Xilinx Spartan3A Board
Table of Contents 1. Introduction 2 2. Methodology 2 2.1. Design 2 2.2. Code 2 2.2.1. VHDL code 2 2.2.2. UCF pins 2 2.2.3. VHDL simulation 2 3. Results 3 3.1. Simulation 3 3.2. Board 4 4. Discussion 4 4.1. Problems 4 4.2. Linux Ubuntu 4 5. Conclusion 4 6. Appendix 5 6.1. Lab1Code.vhl 5…
16-Bit CPU on Logisim
Single Cycle Processor Design ALU Design For the ALU design, Idid not use the built in aritmethic library. Instead Idesigned each tool(adder, subtractor, multiplier and shifter) meyself. Register File Splitter This unit is responsible for the separation of the opcode, Rs, Rt, Rd, shamt and I[0:15] which determines the type of the function….