4-bit Comparator on Xilinx Spartan 3A
The aim of this experiment is to make familiar with the elementary logic gates while designing 4-bit comparator circuits for unsigned and 2’s complement systems. I will design my circuit using Xilinx ISE software as performed in the first experiment. Then I will simulate my circuit behavior and deploy my design to the Prometheus board.
Table of Contents
Aim
The aim of this experiment is to make familiar with the elementary logic gates while designing 4-bit comparator circuits for unsigned and 2’s complement systems. I will design my circuit using Xilinx ISE software as performed in the first experiment. Then I will simulate my circuit behavior and deploy my design to the Prometheus board.
Preliminary Work
I designed the 4 bit comparator using logical gates for the 4 bit unsigned and signed binary number. I used the Logisim program for testing my logic circuit design. I will use the if statements technics for designing this circuit. In other words, I checked the A and B are equal or not and A is bigger than B or not. After that if these are give me “0(not)” than my circuit say that B>A. I use this if , else if, else techniques for my logical design.
Question 1
I used XOR and not gate (XNOR) for checking equality.
Schematic
Test
Equal
Not Equal
Question 2
I used XOR gates for the checking equation and I check the MSB (most significant bits) in A and B if
A AND notB output is equal 1 it is mean A is bigger than B if not next AND check next bits with the checking the most bits equality. I can look into circuit bellow schematic
Schematic
Yellow marked shows the inputs decimals.
Test
Equal
A>B
B>A
Question 3
When I changed the MSB checking AND gate’s not gate this circuit turned to signed. I marked (yellow) which not gate is changed
Schematic
Test
Equal
A>B
B>A
Experimental Work
Methodology
Part1
In this part I implement bellow unsgined comparator design and simulate the magnitude comparator circuit.
Design
Bellow design shows the unsigned magnitude comparator. In this circuit first checking the equality of the bits after that the checking the A is bigger than B or not after that if two condition is not satisfied G-BA (B is bigger than A) output pins give the HIGH(1)
Code
VHDL code
In the MComparator.vhd file at the Appendix 5.1. shows our implementation code for the magnitude comparator circuit. Firstly, I identified inputs and outputs these are; S0, S1, S2, S3, S4, S5, S6, and S7 are inputs and E, GAB, GBA are outputs. After that, I defined the circuit in my bellow codes
“E <= (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0);” This code represent the Equality XNOR gates checking the inputs bits are equal are not. After checking the all bits if all bits same E equals 1.
“GAB <= (S7 AND (NOT S3)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1));” This code represent the checking greater A than B.
“GBA <= ((S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0)) NOR ((S7 AND (NOT S3)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1)));” This code is represent the E NOR GAB its mean if E and GAB is not 1 then GBA is 1
UCF pins
In the Lab2Pins.ucf file at the Appendix 5.2. shows our implementation code for the boards input and outputs.
NET “S7” LOC = “P85”;
NET “S6” LOC = “P88”;
NET “S5” LOC = “P90”;
NET “S4” LOC = “P94”;
NET “S3” LOC = “P4”;
NET “S2” LOC = “P5”;
NET “S1” LOC = “P12”;
NET “S0” LOC = “P15”;
NET “E” LOC = “P13”;
NET “GAB” LOC = “P6”;
NET “GBA” LOC = “P3”;
VHDL simulation
In the Lab2.vhd file at the Appendix 5.3. shows our implementation code for the simulation. In the simulation code I tested some probabilities You can see the result at 3.2.1.1. Simulation.
Part2
In this part I implement bellow signed comparator design and simulate the signed comparator circuit.
Design
Bellow design shows the Signed comparator. In this circuit first checking the equality of the bits after that the checking the A is bigger than B (but first bits must be lesser) or not after that if two condition is not satisfied G-BA (B is bigger than A) output pins give the HIGH(1)
Code
VHDL code
In the SComparator.vhd file at the Appendix 5.4. shows our implementation code for the magnitude comparator circuit. Firstly, I identified inputs and outputs these are; S0, S1, S2, S3, S4, S5, S6, and S7 are inputs and E, GAB, GBA are outputs. After that, I defined the circuit in my bellow codes
“E <= (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0);” This code represent the Equality XNOR gates checking the inputs bits are equal are not. After checking the all bits if all bits same E equals 1.
“GAB <= (S3 AND (NOT S7)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1));” This code represent the checking greater A than B.
“GBA <= ((S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0)) NOR ((S3 AND (NOT S7)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1)));” This code is represent the E NOR GAB its mean if E and GAB is not 1 then GBA is 1
UCF pins
This is the same as like part 1. In the Lab2Pins.ucf file at the Appendix 5.2. shows our implementation code for the boards input and outputs.
NET “S7” LOC = “P85”;
NET “S6” LOC = “P88”;
NET “S5” LOC = “P90”;
NET “S4” LOC = “P94”;
NET “S3” LOC = “P4”;
NET “S2” LOC = “P5”;
NET “S1” LOC = “P12”;
NET “S0” LOC = “P15”;
NET “E” LOC = “P13”;
NET “GAB” LOC = “P6”;
NET “GBA” LOC = “P3”;
VHDL simulation
This is same as Part1. In the Lab2.vhd file at the Appendix 5.3. shows our implementation code for the simulation. In the simulation code I tested some probabilities You can see the result at 3.2.2.1. Simulation.
Results
Part1
Simulation
Board
A[0111] B[0100] E=0 GAB = 1 GBA = 0
A[0000] B[0000] E=1 GAB = 0 GBA = 0
Part2
Simulation
Board
A[1111] B[0100] E=0 GAB = 0 GBA = 1
A[0110] B[1000] E=0 GAB = 1 GBA = 0
A[0110] B[1000] E=0 GAB = 1 GBA = 0
A[1000] B[0000] E=0 GAB = 0 GBA = 1
Conclusion
In this Lab, I learnt the making complex logic circuit in VHDL such as signed and unsigned comparator and also I learn the looking the circuit in the Xilinx. Bellow picture shows my circuit. 
Apendix
MComparator.vhd
———————————————————————————-
— Company:
— Engineer:
—
— Create Date: 09:00:23 03/02/2018
— Design Name:
— Module Name: MComparator – Behavioral
— Project Name:
— Target Devices:
— Tool versions:
— Description:
—
— Dependencies:
—
— Revision:
— Revision 0.01 – File Created
— Additional Comments:
—
———————————————————————————-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;
— Uncomment the following library declaration if instantiating
— any Xilinx primitives in this code.
–library UNISIM;
–use UNISIM.VComponents.all;
entity MComparator is
Port ( S7 : in STD_LOGIC;
S6 : in STD_LOGIC;
S5 : in STD_LOGIC;
S4 : in STD_LOGIC;
S3 : in STD_LOGIC;
S2 : in STD_LOGIC;
S1 : in STD_LOGIC;
S0 : in STD_LOGIC;
E : out STD_LOGIC;
GAB : out STD_LOGIC;
GBA : out STD_LOGIC);
end MComparator;
architecture Behavioral of MComparator is
begin
E <= (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0);
GAB <= (S7 AND (NOT S3)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1));
GBA <= ((S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0)) NOR ((S7 AND (NOT S3)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1)));
end Behavioral;
Lab2Pins.ucf
NET “S7” LOC = “P85”;
NET “S6” LOC = “P88”;
NET “S5” LOC = “P90”;
NET “S4” LOC = “P94”;
NET “S3” LOC = “P4”;
NET “S2” LOC = “P5”;
NET “S1” LOC = “P12”;
NET “S0” LOC = “P15”;
NET “E” LOC = “P13”;
NET “GAB” LOC = “P6”;
NET “GBA” LOC = “P3”;
Lab2Sim.vhd
——————————————————————————–
— Company:
— Engineer:
—
— Create Date: 09:22:51 03/02/2018
— Design Name:
— Module Name: C:/Lab2/SComparator/Lab2Sim.vhd
— Project Name: SComparator
— Target Device:
— Tool versions:
— Description:
—
— VHDL Test Bench Created by ISE for module: SComparator
—
— Dependencies:
—
— Revision:
— Revision 0.01 – File Created
— Additional Comments:
—
— Notes:
— This testbench has been automatically generated using types std_logic and
— std_logic_vector for the ports of the unit under test. Xilinx recommends
— that these types always be used for the top-level I/O of a design in order
— to guarantee that the testbench will bind correctly to the post-implementation
— simulation model.
——————————————————————————–
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–USE ieee.numeric_std.ALL;
ENTITY Lab2Sim IS
END Lab2Sim;
ARCHITECTURE behavior OF Lab2Sim IS
— Component Declaration for the Unit Under Test (UUT)
COMPONENT SComparator
PORT(
S7 : IN std_logic;
S6 : IN std_logic;
S5 : IN std_logic;
S4 : IN std_logic;
S3 : IN std_logic;
S2 : IN std_logic;
S1 : IN std_logic;
S0 : IN std_logic;
E : OUT std_logic;
GAB : OUT std_logic;
GBA : OUT std_logic
);
END COMPONENT;
–Inputs
signal S7 : std_logic := ‘0’;
signal S6 : std_logic := ‘0’;
signal S5 : std_logic := ‘0’;
signal S4 : std_logic := ‘0’;
signal S3 : std_logic := ‘0’;
signal S2 : std_logic := ‘0’;
signal S1 : std_logic := ‘0’;
signal S0 : std_logic := ‘0’;
–Outputs
signal E : std_logic;
signal GAB : std_logic;
signal GBA : std_logic;
— No clocks detected in port list. Replace <clock> below with
— appropriate port name
constant Clock_period : time := 10 ns;
BEGIN
— Instantiate the Unit Under Test (UUT)
uut: SComparator PORT MAP (
S7 => S7,
S6 => S6,
S5 => S5,
S4 => S4,
S3 => S3,
S2 => S2,
S1 => S1,
S0 => S0,
E => E,
GAB => GAB,
GBA => GBA
);
— Clock process definitions
Clock_process :process
begin
S7 <= ‘1’; S6 <= ‘0’; S5 <= ‘0’; S4 <= ‘0’; S3 <= ‘1’; S2 <= ‘0’; S1 <= ‘0’; S0 <= ‘0’;
wait for Clock_period;
S7 <= ‘0’; S6 <= ‘0’; S5 <= ‘0’; S4 <= ‘0’; S3 <= ‘0’; S2 <= ‘0’; S1 <= ‘0’; S0 <= ‘0’;
wait for Clock_period;
S7 <= ‘0’; S6 <= ‘1’; S5 <= ‘1’; S4 <= ‘0’; S3 <= ‘1’; S2 <= ‘0’; S1 <= ‘0’; S0 <= ‘0’;
wait for Clock_period;
S7 <= ‘1’; S6 <= ‘0’; S5 <= ‘0’; S4 <= ‘0’; S3 <= ‘0’; S2 <= ‘1’; S1 <= ‘0’; S0 <= ‘0’;
wait for Clock_period;
S7 <= ‘0’; S6 <= ‘0’; S5 <= ‘1’; S4 <= ‘0’; S3 <= ‘1’; S2 <= ‘0’; S1 <= ‘0’; S0 <= ‘0’;
wait for Clock_period;
S7 <= ‘1’; S6 <= ‘1’; S5 <= ‘1’; S4 <= ‘0’; S3 <= ‘0’; S2 <= ‘1’; S1 <= ‘0’; S0 <= ‘0’;
wait for Clock_period;
S7 <= ‘0’; S6 <= ‘0’; S5 <= ‘0’; S4 <= ‘1’; S3 <= ‘1’; S2 <= ‘0’; S1 <= ‘0’; S0 <= ‘0’; — Return to initial value
wait;
end process;
— Stimulus process
stim_proc: process
begin
— hold reset state for 100 ns.
wait for 100 ns;
wait for Clock_period*10;
— insert stimulus here
wait;
end process;
END;
SComparator.vhd
———————————————————————————-
— Company:
— Engineer:
—
— Create Date: 09:00:23 03/02/2018
— Design Name:
— Module Name: SComparator – Behavioral
— Project Name:
— Target Devices:
— Tool versions:
— Description:
—
— Dependencies:
—
— Revision:
— Revision 0.01 – File Created
— Additional Comments:
—
———————————————————————————-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;
— Uncomment the following library declaration if instantiating
— any Xilinx primitives in this code.
–library UNISIM;
–use UNISIM.VComponents.all;
entity SComparator is
Port ( S7 : in STD_LOGIC;
S6 : in STD_LOGIC;
S5 : in STD_LOGIC;
S4 : in STD_LOGIC;
S3 : in STD_LOGIC;
S2 : in STD_LOGIC;
S1 : in STD_LOGIC;
S0 : in STD_LOGIC;
E : out STD_LOGIC;
GAB : out STD_LOGIC;
GBA : out STD_LOGIC);
end SComparator;
architecture Behavioral of SComparator is
begin
E <= (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0);
GAB <= (S3 AND (NOT S7)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1));
GBA <= ((S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1) AND (S4 XNOR S0)) NOR ((S7 AND (NOT S3)) OR (S6 AND (NOT S2) AND (S7 XNOR S3)) OR (S5 AND (NOT S1) AND (S7 XNOR S3) AND (S6 XNOR S2)) OR (S4 AND (NOT S0) AND (S7 XNOR S3) AND (S6 XNOR S2) AND (S5 XNOR S1)));
end Behavioral;