Aim

Aim of the project is to design a digital accumulator calculator as a synchronous sequential circuit with the following functionalities:

• Taking input as a single 8-bit binary number in 2’s complement system and accumulating (computing and storing) one of the six selected operations between an 8-bit accumulator register and the input into the accumulator register,

• Having three arithmetic operations: addition, subtraction and negation (2’s complement),

• Having three logic operations: bitwise AND, OR and XOR,

• Displaying accumulated result on the 7-segment display in decimal using 3 digits and sign (for negative numbers only),

• Displaying accumulated result on the LEDs as an 8-bit binary output in 2’s complement system.

Preliminary Work

Task 1

Watched the video bellow link

Task2

Algorithm & State Diagram

State Table

A	B	Start	Pass	A(t+1)	B(t+1)
0	0	0	X	0	0
		1	X	0	1
0	1	X	0	0	1
		X	1	1	1
1	1	0	X	0	0
		1	X	1	1

K-Maps

A(t+1)

AB\SP	00	01	11	10
00
01		1	1
11			1	1
10	X	X	X	X

AS + A’BP

B(t+1)

AB\SP	00	01	11	10
00			1	1
01	1	1	1	1
11			1	1
10	X	X	X	X

A’B+S

Design

Implementation

In this project, I implement my FSM design for the DAC. I use state diagram (2.2.1) and table (2.2.2). In the code these statements are ; Start, Compute, ComputeEnd

Code

My code have two side one of them is VHD and another is pins configuration UCF file

VHD

First of the code I initialize input and outputs ports then I initialize machine states then I convert to 12 bit number to bit BCD numbers with using the for loop in to_BCD function. And I implement my statement with using case conditions. You can find my code in the Appendix 1 (Lab5Code.vhd).

UCF

In the .ucf file have my pins address for the Spartan3A processor and board. Also you can find the code in Appendix 2 (Lab5.ucf)

Board

Bellow figure shows my board functions location.

Conclusion

In this project I learn to implement state machine to VHDL board. And I learned to how to convert binary to BCD number

Appendix

Lab5Code.vhd

 

Lab5.ucf