Aim
Aim of the project is to design a digital accumulator calculator as a synchronous sequential circuit with the following functionalities:
• Taking input as a single 8-bit binary number in 2’s complement system and accumulating (computing and storing) one of the six selected operations between an 8-bit accumulator register and the input into the accumulator register,
• Having three arithmetic operations: addition, subtraction and negation (2’s complement),
• Having three logic operations: bitwise AND, OR and XOR,
• Displaying accumulated result on the 7-segment display in decimal using 3 digits and sign (for negative numbers only),
• Displaying accumulated result on the LEDs as an 8-bit binary output in 2’s complement system.
Preliminary Work
Task 1
Watched the video bellow link
Task2
Algorithm & State Diagram
State Table
A | B | Start | Pass | A(t+1) | B(t+1) |
0 | 0 | 0 | X | 0 | 0 |
1 | X | 0 | 1 | ||
0 | 1 | X | 0 | 0 | 1 |
X | 1 | 1 | 1 | ||
1 | 1 | 0 | X | 0 | 0 |
1 | X | 1 | 1 |
K-Maps
A(t+1)
AB\SP | 00 | 01 | 11 | 10 |
00 | ||||
01 | 1 | 1 | ||
11 | 1 | 1 | ||
10 | X | X | X | X |
AS + A’BP
B(t+1)
AB\SP | 00 | 01 | 11 | 10 |
00 | 1 | 1 | ||
01 | 1 | 1 | 1 | 1 |
11 | 1 | 1 | ||
10 | X | X | X | X |
A’B+S
Design
Implementation
In this project, I implement my FSM design for the DAC. I use state diagram (2.2.1) and table (2.2.2). In the code these statements are ; Start, Compute, ComputeEnd
Code
My code have two side one of them is VHD and another is pins configuration UCF file
VHD
First of the code I initialize input and outputs ports then I initialize machine states then I convert to 12 bit number to bit BCD numbers with using the for loop in to_BCD function. And I implement my statement with using case conditions. You can find my code in the Appendix 1 (Lab5Code.vhd).
UCF
In the .ucf file have my pins address for the Spartan3A processor and board. Also you can find the code in Appendix 2 (Lab5.ucf)
Board
Bellow figure shows my board functions location.
Conclusion
In this project I learn to implement state machine to VHDL board. And I learned to how to convert binary to BCD number
Appendix
Lab5Code.vhd
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---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity Lab5 is Generic (N : INTEGER:=50*10**6; M: INTEGER:=65536); Port ( MCLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR(7 downto 0); Sub : in STD_LOGIC; Add : in STD_LOGIC; Neg : in STD_LOGIC; Cxor : in STD_LOGIC; Cor : in STD_LOGIC; Cand : in STD_LOGIC; Result1 : out STD_LOGIC_VECTOR(7 downto 0); SevenSegment : out STD_LOGIC_VECTOR (6 downto 0); Anodes : out STD_LOGIC_VECTOR (7 downto 0)); end Lab5; architecture Behavioral of Lab5 is signal CLK_DIV : STD_LOGIC; signal X: STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- FSM with 3 states constant START: STD_LOGIC_VECTOR(1 downto 0) := "00"; constant compute: STD_LOGIC_VECTOR(1 downto 0) := "01"; constant ComputeEnd: STD_LOGIC_VECTOR(1 downto 0) := "11"; -- State variable with 3 flip-flops signal State: STD_LOGIC_VECTOR(1 downto 0) := "00"; signal Out1: STD_LOGIC_VECTOR (3 downto 0); signal Out2: STD_LOGIC_VECTOR (3 downto 0); signal Out3: STD_LOGIC_VECTOR (3 downto 0); signal Result1B: STD_LOGIC_VECTOR (7 downto 0); signal Result1BCD:STD_LOGIC_VECTOR(11 downto 0); function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is variable i : integer:=0; variable bcd : std_logic_vector(11 downto 0) := (others => '0'); variable bint : std_logic_vector(7 downto 0) := bin; begin for i in 0 to 7 loop bcd(11 downto 1) := bcd(10 downto 0); bcd(0) := bint(7); bint(7 downto 1) := bint(6 downto 0); bint(0) :='0'; if(i < 7 and bcd(3 downto 0) > "0100") then bcd(3 downto 0) := bcd(3 downto 0) + "0011"; end if; if(i < 7 and bcd(7 downto 4) > "0100") then bcd(7 downto 4) := bcd(7 downto 4) + "0011"; end if; if(i < 7 and bcd(11 downto 8) > "0100") then bcd(11 downto 8) := bcd(11 downto 8) + "0011"; end if; end loop; return bcd; end to_bcd; begin Result1BCD <= to_bcd(Result1B); Out1 <= Result1BCD(11 downto 8); Out2 <= Result1BCD(7 downto 4); Out3 <= Result1BCD(3 downto 0); process(MCLK) variable Counter : INTEGER range 0 to N; begin if rising_edge(MCLK) then Counter := Counter + 1; if (Counter = N/15-1) then Counter := 0; CLK_DIV <= not CLK_DIV; end if; end if; end process; process(CLK_DIV) begin if rising_edge(CLK_DIV) then case State is when START => if (Sub='1' and Add='0' and Neg='0' and Cxor='0' and Cor='0' and Cand='0') then State <= compute; elsif (Sub='0' and Add='1' and Neg='0' and Cxor='0' and Cor='0' and Cand='0') then State <= compute; elsif (Sub='0' and Add='0' and Neg='1' and Cxor='0' and Cor='0' and Cand='0') then State <= compute; elsif (Sub='0' and Add='0' and Neg='0' and Cxor='1' and Cor='0' and Cand='0') then State <= compute; elsif (Sub='0' and Add='0' and Neg='0' and Cxor='0' and Cor='1' and Cand='0') then State <= compute; elsif (Sub='0' and Add='0' and Neg='0' and Cxor='0' and Cor='0' and Cand='1') then State <= compute; else State <= START; end if; when compute => if ( Sub='1' and Add='0' and Neg='0' and Cxor='0' and Cor='0' and Cand='0') then X <= X + ((not A) + 1); State <= ComputeEnd; elsif (Sub='0' and Add='1' and Neg='0' and Cxor='0' and Cor='0' and Cand='0') then X <= X + A; State <= ComputeEnd; elsif (Sub='0' and Add='0' and Neg='1' and Cxor='0' and Cor='0' and Cand='0') then X <= (not X) + 1; State <= ComputeEnd; elsif (Sub='0' and Add='0' and Neg='0' and Cxor='1' and Cor='0' and Cand='0') then X <= X xor A; State <= ComputeEnd; elsif (Sub='0' and Add='0' and Neg='0' and Cxor='0' and Cor='1' and Cand='0') then X <= X or A; State <= ComputeEnd; elsif (Sub='0' and Add='0' and Neg='0' and Cxor='0' and Cor='0' and Cand='1') then X <= X and A; State <= ComputeEnd; end if; when ComputeEnd => if(X(7) = '1') then Result1B <= (not X) + 1; else Result1B <= X; end if; Result1 <= X; State <= START; when others => State <= START; end case; end if; end process; process(MCLK) variable Counter : INTEGER range 0 to M; begin if(rising_edge(MCLK)) then Counter :=Counter+1; if (Counter mod M = 0) then if(Out3="0000") then Anodes <= "11111110"; SevenSegment <= "0000001"; -- "0" elsif (Out3="0001") then Anodes <= "11111110"; SevenSegment <= "1001111"; -- "1" elsif (Out3="0010") then Anodes <= "11111110"; SevenSegment <= "0010010"; -- "2" elsif (Out3="0011") then Anodes <= "11111110"; SevenSegment <= "0000110"; -- "3" elsif (Out3="0100") then Anodes <= "11111110"; SevenSegment <= "1001100"; -- "4" elsif (Out3="0101") then Anodes <= "11111110"; SevenSegment <= "0100100"; -- "5" elsif (Out3="0110") then Anodes <= "11111110"; SevenSegment <= "0100000"; -- "6" elsif (Out3="0111") then Anodes <= "11111110"; SevenSegment <= "0001111"; -- "7" elsif (Out3="1000") then Anodes <= "11111110"; SevenSegment <= "0000000"; -- "8" elsif (Out3="1001") then Anodes <= "11111110"; SevenSegment <= "0000100"; -- "9" end if; elsif (Counter mod M = 1*M/8) then if(Out2="0000") then Anodes <= "11111101"; SevenSegment <= "0000001"; -- "0" elsif (Out2="0001") then Anodes <= "11111101"; SevenSegment <= "1001111"; -- "1" elsif (Out2="0010") then Anodes <= "11111101"; SevenSegment <= "0010010"; -- "2" elsif (Out2="0011") then Anodes <= "11111101"; SevenSegment <= "0000110"; -- "3" elsif (Out2="0100") then Anodes <= "11111101"; SevenSegment <= "1001100"; -- "4" elsif (Out2="0101") then Anodes <= "11111101"; SevenSegment <= "0100100"; -- "5" elsif (Out2="0110") then Anodes <= "11111101"; SevenSegment <= "0100000"; -- "6" elsif (Out2="0111") then Anodes <= "11111101"; SevenSegment <= "0001111"; -- "7" elsif (Out2="1000") then Anodes <= "11111101"; SevenSegment <= "0000000"; -- "8" elsif (Out2="1001") then Anodes <= "11111101"; SevenSegment <= "0000100"; -- "9" end if; elsif (Counter mod M = 2*M/8) then if(Out1="0000") then Anodes <= "11111011"; SevenSegment <= "0000001"; -- "0" elsif (Out1="0001") then Anodes <= "11111011"; SevenSegment <= "1001111"; -- "1" elsif (Out1="0010") then Anodes <= "11111011"; SevenSegment <= "0010010"; -- "2" elsif (Out1="0011") then Anodes <= "11111011"; SevenSegment <= "0000110"; -- "3" elsif (Out1="0100") then Anodes <= "11111011"; SevenSegment <= "1001100"; -- "4" elsif (Out1="0101") then Anodes <= "11111011"; SevenSegment <= "0100100"; -- "5" elsif (Out1="0110") then Anodes <= "11111011"; SevenSegment <= "0100000"; -- "6" elsif (Out1="0111") then Anodes <= "11111011"; SevenSegment <= "0001111"; -- "7" elsif (Out1="1000") then Anodes <= "11111011"; SevenSegment <= "0000000"; -- "8" elsif (Out1="1001") then Anodes <= "11111011"; SevenSegment <= "0000100"; -- "9" end if; elsif (Counter mod M = 3*M/8) then if (X(7)='0') then Anodes <= "11110111"; SevenSegment <= "1111111"; else Anodes <= "11110111"; SevenSegment <= "1111110"; end if; end if; end if; end process; end Behavioral; |
Lab5.ucf
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NET "MCLK" LOC = "P40"; NET "Sub" LOC = "P37"; NET "Add" LOC = "P32"; NET "Neg" LOC = "P33"; NET "Cxor" LOC = "P36"; NET "Cor" LOC = "P35"; NET "Cand" LOC = "P34"; NET "A<0>" LOC = "P15"; NET "A<1>" LOC = "P12"; NET "A<2>" LOC = "P5"; NET "A<3>" LOC = "P4"; NET "A<4>" LOC = "P94"; NET "A<5>" LOC = "P90"; NET "A<6>" LOC = "P88"; NET "A<7>" LOC = "P85"; NET "Result1<0>" LOC = "P16"; NET "Result1<1>" LOC = "P13"; NET "Result1<2>" LOC = "P6"; NET "Result1<3>" LOC = "P3"; NET "Result1<4>" LOC = "P93"; NET "Result1<5>" LOC = "P89"; NET "Result1<6>" LOC = "P86"; NET "Result1<7>" LOC = "P84"; NET "Anodes<0>" LOC = "P50" ; NET "Anodes<1>" LOC = "P49" ; NET "Anodes<2>" LOC = "P52" ; NET "Anodes<3>" LOC = "P56" ; NET "Anodes<4>" LOC = "P59" ; NET "Anodes<5>" LOC = "P57" ; NET "Anodes<6>" LOC = "P60" ; NET "Anodes<7>" LOC = "P61" ; NET "SevenSegment<0>" LOC = "P64" ; NET "SevenSegment<1>" LOC = "P98" ; NET "SevenSegment<2>" LOC = "P73" ; NET "SevenSegment<3>" LOC = "P72" ; NET "SevenSegment<4>" LOC = "P65" ; NET "SevenSegment<5>" LOC = "P62" ; NET "SevenSegment<6>" LOC = "P71" ; |