Aim
In this lab aims are designing a sequential circuit for LED pattern animations with control inputs and status output functions, and implementing the sequential circuit on FPGA and also experimentally check functionality of the sequential circuit.
Post Report
Led Display
Algorithm
In my algorithm I create two if condition in my specific process. This if conditions are direction of the lights for turning on. I implement a 10bit array and one of them is 1 others are 0. For example when first light is on binary array is like “0000000001”. Then I slide “1” to next bit to decided direction. When the “1” is in the MSB and then direction is changed. Also same process happen for the other direction. All code is in the Appendix
Code
Bellow code shows my algorithm for the sliding operation. “dst” is a direction bit if it is are “0” direction is right to left when “1” goes to end of the bit “dst” updated “1”. Also If each side button pressed when “1” in the LSB or MSB score increase 1.
process(CLK_DIV)
begin
if rising_edge(CLK_DIV) then
if(dst = ‘0’) then
LED_reg <= LED_reg(8 downto 0) & ‘0’;
if(LED_reg(8)=’1′) then
dst <= ‘1’;
if(X1 = ‘1’) then
score <= score + 1;
end if;
end if;
elsif (dst = ‘1’) then
LED_reg <= ‘0’ & LED_reg(9 downto 1);
if(LED_reg(1) =’1′) then
dst <= not dst;
if(X2 = ‘1’) then
score <= score +1;
end if;
end if;
end if;
end if;
end process;
LED <= LED_reg;
Ball Catching Game
Seven Segment
For the scoring table I use the Seven segment display. I incerement the score when pressed the button exact same time to led turned on. Score increase 1.
Code
Bellow show the displaying the result of the score end is updated when score variable change.
process(score)
begin
case score is
when “0000” => SevenSegment <= “0000001”; — “0”
when “0001” => SevenSegment <= “1001111”; — “1”
when “0010” => SevenSegment <= “0010010”; — “2”
when “0011” => SevenSegment <= “0000110”; — “3”
when “0100” => SevenSegment <= “1001100”; — “4”
when “0101” => SevenSegment <= “0100100”; — “5”
when “0110” => SevenSegment <= “0100000”; — “6”
when “0111” => SevenSegment <= “0001101”; — “7”
when “1000” => SevenSegment <= “0000000”; — “8”
when “1001” => SevenSegment <= “0001101”; — “9”
when “1010” => SevenSegment <= “0000010”; — a
when “1011” => SevenSegment <= “1100000”; — b
when “1100” => SevenSegment <= “0110001”; — C
when “1101” => SevenSegment <= “1000010”; — d
when “1110” => SevenSegment <= “0110000”; — E
when “1111” => SevenSegment <= “0111000”; — F
when others => SevenSegment <= “1111111”; — F
end case;
end process;
Preliminary Work
Task 1
I watched the tutorial which is given on manual
Task2
Sequantial Table
A | B | C | A(t+1) | B(t+1) | C(t+1) |
0 | 0 | X | 0 | 1 | 1 |
0 | 1 | 1 | 1 | 0 | 1 |
1 | 0 | 1 | 1 | 1 | 0 |
1 | 1 | X | 1 | 0 | 0 |
1 | 0 | 0 | 0 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 |
K-Maps
A(t+1)
C\AB | 00 | 01 | 11 | 10 |
0 | 1 | |||
1 | 1 | 1 | 1 |
AB + CA + CB
B(t+1)
C\AB | 00 | 01 | 11 | 10 |
0 | 1 | 1 | ||
1 | 1 | 1 |
B’
C(t+1)
C\AB | 00 | 01 | 11 | 10 |
0 | 1 | 1 | ||
1 | 1 | 1 |
A’
Design
Task 3
Sequantial Table
A | B | X1 | X2 | OUTPUT |
0 | 0 | 1 | X | 1 |
0 | 0 | 0 | X | 0 |
0 | 1 | X | X | 0 |
0 | 1 | X | X | 0 |
1 | 1 | X | 1 | 1 |
1 | 1 | X | 0 | 0 |
1 | 0 | X | X | 0 |
1 | 0 | X | X | 0 |
K-Maps
X1X2\AB | 00 | 01 | 11 | 10 |
00 | ||||
01 | 1 | |||
11 | 1 | 1 | ||
10 | 1 |
ABX2 + A’B’X1
Design
Task4
I use the D-flip flop for the counter and this is my Counter design
Full Design
Full Design of my works and also I upload my simulation (Logisim file)
Appendix
Vhdl
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---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 07:34:53 03/30/2018 -- Design Name: -- Module Name: Lab4Code - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Lab4Code is Generic(N:INTEGER:=10*10**6); Port(MCLK : in STD_LOGIC; X1 : in STD_LOGIC; X2 : in STD_LOGIC; SevenSegment : out STD_LOGIC_VECTOR (6 downto 0); LED : out STD_LOGIC_VECTOR(9 downto 0)); end Lab4Code; architecture Behavioral of Lab4Code is signal CLK_DIV : STD_LOGIC; signal LED_reg : std_logic_vector(9 downto 0):="0000000001"; signal dst : STD_LOGIC := '0'; signal score : std_logic_vector(3 downto 0) := "0000"; begin process(MCLK) variable Counter : INTEGER range 0 to N; begin if rising_edge(MCLK) then Counter := Counter + 1; if (Counter = N/1-1) then Counter := 0; CLK_DIV <= not CLK_DIV; end if; end if; end process; process(CLK_DIV) begin if rising_edge(CLK_DIV) then if(dst = '0') then LED_reg <= LED_reg(8 downto 0) & '0'; if(LED_reg(8)='1') then dst <= '1'; if(X1 = '1') then score <= score + 1; end if; end if; elsif (dst = '1') then LED_reg <= '0' & LED_reg(9 downto 1); if(LED_reg(1) ='1') then dst <= not dst; if(X2 = '1') then score <= score +1; end if; end if; end if; end if; end process; LED <= LED_reg; process(score) begin case score is when "0000" => SevenSegment <= "0000001"; -- "0" when "0001" => SevenSegment <= "1001111"; -- "1" when "0010" => SevenSegment <= "0010010"; -- "2" when "0011" => SevenSegment <= "0000110"; -- "3" when "0100" => SevenSegment <= "1001100"; -- "4" when "0101" => SevenSegment <= "0100100"; -- "5" when "0110" => SevenSegment <= "0100000"; -- "6" when "0111" => SevenSegment <= "0001101"; -- "7" when "1000" => SevenSegment <= "0000000"; -- "8" when "1001" => SevenSegment <= "0001101"; -- "9" when "1010" => SevenSegment <= "0000010"; -- a when "1011" => SevenSegment <= "1100000"; -- b when "1100" => SevenSegment <= "0110001"; -- C when "1101" => SevenSegment <= "1000010"; -- d when "1110" => SevenSegment <= "0110000"; -- E when "1111" => SevenSegment <= "0111000"; -- F when others => SevenSegment <= "1111111"; -- F end case; end process; end Behavioral; |
Pins (ucf)
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NET "MCLK" LOC = "P40" ; NET "LED<0>" LOC = "P16" ; NET "LED<1>" LOC = "P13" ; NET "LED<2>" LOC = "P6" ; NET "LED<3>" LOC = "P3" ; NET "LED<4>" LOC = "P93" ; NET "LED<5>" LOC = "P89" ; NET "LED<6>" LOC = "P86" ; NET "LED<7>" LOC = "P84" ; NET "LED<8>" LOC = "P83" ; NET "LED<9>" LOC = "P77" ; NET "X2" LOC = "P34"; NET "X1" LOC = "P35"; NET "SevenSegment<0>" LOC = "P64" ; NET "SevenSegment<1>" LOC = "P98" ; NET "SevenSegment<2>" LOC = "P73" ; NET "SevenSegment<3>" LOC = "P72" ; NET "SevenSegment<4>" LOC = "P65" ; NET "SevenSegment<5>" LOC = "P62" ; NET "SevenSegment<6>" LOC = "P71" ; |