Aim

In this lab aims are designing a sequential circuit for LED pattern animations with control inputs and status output functions, and implementing the sequential circuit on FPGA and also experimentally check functionality of the sequential circuit.

Post Report

Led Display

Algorithm

In my algorithm I create two if condition in my specific process. This if conditions are direction of the lights for turning on. I implement a 10bit array and one of them is 1 others are 0. For example when first light is on binary array is like “0000000001”. Then I slide “1” to next bit to decided direction. When the “1” is in the MSB and then direction is changed. Also same process happen for the other direction. All code is in the Appendix

Code

Bellow code shows my algorithm for the sliding operation. “dst” is a direction bit if it is are “0” direction is right to left when “1” goes to end of the bit “dst” updated “1”. Also If each side button pressed when “1” in the LSB or MSB score increase 1.

process(CLK_DIV)
begin
if rising_edge(CLK_DIV) then
if(dst = ‘0’) then
LED_reg <= LED_reg(8 downto 0) & ‘0’;
if(LED_reg(8)=’1′) then
dst <= ‘1’;
if(X1 = ‘1’) then
score <= score + 1;
end if;
end if;
elsif (dst = ‘1’) then
LED_reg <= ‘0’ & LED_reg(9 downto 1);
if(LED_reg(1) =’1′) then
dst <= not dst;
if(X2 = ‘1’) then
score <= score +1;
end if;
end if;
end if;
end if;
end process;
LED <= LED_reg;

Ball Catching Game

Seven Segment

For the scoring table I use the Seven segment display. I incerement the score when pressed the button exact same time to led turned on. Score increase 1.

Code

Bellow show the displaying the result of the score end is updated when score variable change.

process(score)
begin
case score is
when “0000” => SevenSegment <= “0000001”; — “0”
when “0001” => SevenSegment <= “1001111”; — “1”
when “0010” => SevenSegment <= “0010010”; — “2”
when “0011” => SevenSegment <= “0000110”; — “3”
when “0100” => SevenSegment <= “1001100”; — “4”
when “0101” => SevenSegment <= “0100100”; — “5”
when “0110” => SevenSegment <= “0100000”; — “6”
when “0111” => SevenSegment <= “0001101”; — “7”
when “1000” => SevenSegment <= “0000000”; — “8”
when “1001” => SevenSegment <= “0001101”; — “9”
when “1010” => SevenSegment <= “0000010”; — a
when “1011” => SevenSegment <= “1100000”; — b
when “1100” => SevenSegment <= “0110001”; — C
when “1101” => SevenSegment <= “1000010”; — d
when “1110” => SevenSegment <= “0110000”; — E
when “1111” => SevenSegment <= “0111000”; — F
when others => SevenSegment <= “1111111”; — F
end case;
end process;

Preliminary Work

Task 1

I watched the tutorial which is given on manual

Task2

Sequantial Table

A	B	C	A(t+1)	B(t+1)	C(t+1)
0	0	X	0	1	1
0	1	1	1	0	1
1	0	1	1	1	0
1	1	X	1	0	0
1	0	0	0	1	0
0	1	0	0	0	1

K-Maps

A(t+1)

C\AB	00	01	11	10
0			1
1		1	1	1

AB + CA + CB

B(t+1)

C\AB	00	01	11	10
0	1			1
1	1			1

B’

C(t+1)

C\AB	00	01	11	10
0	1	1
1	1	1

A’

Design

Task 3

Sequantial Table

A	B	X1	X2	OUTPUT
0	0	1	X	1
0	0	0	X	0
0	1	X	X	0
0	1	X	X	0
1	1	X	1	1
1	1	X	0	0
1	0	X	X	0
1	0	X	X	0

K-Maps

X1X2\AB	00	01	11	10
00
01			1
11	1		1
10	1

ABX2 + A’B’X1

Design

Task4

I use the D-flip flop for the counter and this is my Counter design

Full Design

Full Design of my works and also I upload my simulation (Logisim file)

Appendix

Vhdl

 

Pins (ucf)