Aim
In this lab aim is the design 4- bit Arithmetic and Logic Unit (ALU) and implement the ALU on FPGA using modular design, after that, experimentally check the operation of the ALU on Spartan board
Implementation
Mux
I designed the multiplexers. These are 2 to 1 , 4 to 1 and 2 to 1 (4-bit) with using 2 to 1 Mux. I use 2 to 1 Mux for the selected the output of the ALU which is Logical or Arihtmetical.
2 to 1
4 to 1
I use 4 to 1 mux for opcode for the my ALU. Its means, I selected the operation with using this mux.
2 to 1 (4-bit input)
I use the 1 bit Mux for the making the 4 bit Mux.
Logic Unit
Firstly I design 1 bit Logic Unit.I use the divide and conquer method. After that, I design 4 bit Logic Unit with using 4-1 Mux.
1-bit Logic Unit
Bellow figure shows the my implemantetion for the one bit Logic unit.
4-bit Logic Unit
Below figure shows how to implement the bit Logic gate with using one bit logic. Each bits of the input goes in the different logic unit with order. After that I collect the outputs with same order.
Arithmetic Unit
In this part, My purpose of the design the Arithmetic Unit. Firstly, I design the Full adder and 1 bit Arithmetic Unit. Then, I design the 4-bit Arithmetic Unit.
Full Adder
Bellows figures shows my Full Adder implementation. This is 1 bit
1-bit Arithmetic Unit
Bellows figures shows my 1-bit arithmetic unit implementation. After that, I will design 4-bit Arihtmetic Unit with using this 1 bit Arithmetic Unit.
4-bit Arithmetic Unit
I use 1 bit Arihtmetic Unit. First bits inputs of the first 1 bit arithmetic units and outputs of the this Unit are F0 and Cout1. Cout1 will be inputs of the seconds bits Arihtmetic Unit. Contiune with this order I created 4-bit Arithmetic Unit.
Seven Segment
In this question I design the seven segment and after that I design the all ALU design . But I don’t use this method in Xilinx . I use more simple methods.
Conditions
A
B
C
D
E
F
G
Seven Segment
ALU
Bellow figure show the my ALU. And I tested the Logisim before the Lab. I used this methodology In the Xilinx.
Xilinx
Code
Firstly I defined the inputs and outputs of the design. After that I created the 3 signal. These are LOGut, ARTout and const. After that. I implement my 1-bit ALU design.
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const <= ‘0’;
LOGout <=(((not S0) AND (not S1) AND (A AND B)) OR ((S0) AND (not S1) AND (A OR B))) OR (((not S0) AND (S1) AND (A XOR B)) OR ((S0) AND (S1) AND (A XNOR B)));
ARToutF <=(((not S0) AND (not S1) AND ((A XOR const) XOR Cin)) OR ((S0) AND (not S1) AND ((A XOR B) XOR Cin))) OR (((not S0) AND (S1) AND ((A XOR (not B)) XOR Cin)) OR ((S0) AND (S1) AND (((not A) XOR B) XOR Cin)));
Cout <=(((not S0) AND (not S1) AND ((A AND const) OR ((A XOR const)AND Cin))) OR ((S0) AND (not S1) AND ((A AND B) OR ((A XOR B)AND Cin)))) OR (((not S0) AND (S1) AND ((A AND not (B)) OR ((A XOR (not B))AND Cin))) OR ((S0) AND (S1) AND (((not A) AND B) OR (((not A) XOR B)AND Cin))));
F <=((not M) AND LOGout) OR (M AND ARToutF);
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Pins
In this code I defined the pinouts of the board with inputs and outputs
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NET “A” LOC = “P15”;
NET “B” LOC = “P12”;
NET “Cin” LOC = “P5”;
NET “M” LOC = “P78”;
NET “S1” LOC = “P82”;
NET “S0” LOC = “P85”;
NET “F” LOC = “P16”;
NET “Cout” LOC = “P77”;
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4-bit
Code
In this code I implement my 4-bit ALU before created on Logisim.
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entity Lab3_Part2_Code is
Port ( M : in STD_LOGIC;
S1 : in STD_LOGIC;
S0 : in STD_LOGIC;
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
Signbit : out STD_LOGIC;
SevenSegment : out STD_LOGIC_VECTOR(6 downto 0);
F : out STD_LOGIC_VECTOR(3 downto 0));
end Lab3_Part2_Code;
architecture Behavioral of Lab3_Part2_Code is
signal LOGout : STD_LOGIC_VECTOR(3 downto 0); — Intermediate signal
signal ARToutF : STD_LOGIC_VECTOR(3 downto 0); — Intermediate signal
signal const : STD_LOGIC; — Intermediate signal
signal Cout0 : STD_LOGIC; — Intermediate signal
signal Cout1 : STD_LOGIC; — Intermediate signal
signal Cout2 : STD_LOGIC; — Intermediate signal
begin
const <= ‘0’;
LOGout(0) <=(((not S0) AND (not S1) AND (A(0) AND B(0))) OR ((S0) AND (not S1) AND (A(0) OR B(0)))) OR (((not S0) AND (S1) AND (A(0) XOR B(0))) OR ((S0) AND (S1) AND (A(0) XNOR B(0))));
LOGout(1) <=(((not S0) AND (not S1) AND (A(1) AND B(1))) OR ((S0) AND (not S1) AND (A(1) OR B(1)))) OR (((not S0) AND (S1) AND (A(1) XOR B(1))) OR ((S0) AND (S1) AND (A(1) XNOR B(1))));
LOGout(2) <=(((not S0) AND (not S1) AND (A(2) AND B(2))) OR ((S0) AND (not S1) AND (A(2) OR B(2)))) OR (((not S0) AND (S1) AND (A(2) XOR B(2))) OR ((S0) AND (S1) AND (A(2) XNOR B(2))));
LOGout(3) <=(((not S0) AND (not S1) AND (A(3) AND B(3))) OR ((S0) AND (not S1) AND (A(3) OR B(3)))) OR (((not S0) AND (S1) AND (A(3) XOR B(3))) OR ((S0) AND (S1) AND (A(3) XNOR B(3))));
ARToutF(0) <=(((not S0) AND (not S1) AND ((A(0) XOR const) XOR Cin)) OR ((S0) AND (not S1) AND ((A(0) XOR B(0)) XOR Cin))) OR (((not S0) AND (S1) AND ((A(0) XOR (not B(0))) XOR Cin)) OR ((S0) AND (S1) AND (((not A(0)) XOR B(0)) XOR Cin)));
Cout0 <=(((not S0) AND (not S1) AND ((A(0) AND const) OR ((A(0) XOR const)AND Cin))) OR ((S0) AND (not S1) AND ((A(0) AND B(0)) OR ((A(0) XOR B(0))AND Cin)))) OR (((not S0) AND (S1) AND ((A(0) AND (not B(0))) OR ((A(0) XOR (not B(0)))AND Cin))) OR ((S0) AND (S1) AND (((not A(0)) AND B(0)) OR (((not A(0)) XOR B(0))AND Cin))));
ARToutF(1) <=(((not S0) AND (not S1) AND ((A(1) XOR const) XOR Cout0)) OR ((S0) AND (not S1) AND ((A(1) XOR B(1)) XOR Cout0))) OR (((not S0) AND (S1) AND ((A(1) XOR (not B(1))) XOR Cout0)) OR ((S0) AND (S1) AND (((not A(1)) XOR B(1)) XOR Cout0)));
Cout1 <=(((not S0) AND (not S1) AND ((A(1) AND const) OR ((A(1) XOR const)AND Cout0))) OR ((S0) AND (not S1) AND ((A(1) AND B(1)) OR ((A(1) XOR B(1))AND Cout0)))) OR (((not S0) AND (S1) AND ((A(1) AND (not B(1))) OR ((A(1) XOR (not B(1)))AND Cout0))) OR ((S0) AND (S1) AND (((not A(1)) AND B(1)) OR (((not A(1)) XOR B(1))AND Cout0))));
ARToutF(2) <=(((not S0) AND (not S1) AND ((A(2) XOR const) XOR Cout1)) OR ((S0) AND (not S1) AND ((A(2) XOR B(2)) XOR Cout1))) OR (((not S0) AND (S1) AND ((A(2) XOR (not B(2))) XOR Cout1)) OR ((S0) AND (S1) AND (((not A(2)) XOR B(2)) XOR Cout1)));
Cout2 <=(((not S0) AND (not S1) AND ((A(2) AND const) OR ((A(2) XOR const)AND Cout1))) OR ((S0) AND (not S1) AND ((A(2) AND B(2)) OR ((A(2) XOR B(2))AND Cout1)))) OR (((not S0) AND (S1) AND ((A(2) AND (not B(2))) OR ((A(2) XOR (not B(2)))AND Cout1))) OR ((S0) AND (S1) AND (((not A(2)) AND B(2)) OR (((not A(2)) XOR B(2))AND Cout1))));
ARToutF(3) <=(((not S0) AND (not S1) AND ((A(3) XOR const) XOR Cout2)) OR ((S0) AND (not S1) AND ((A(3) XOR B(3)) XOR Cout2))) OR (((not S0) AND (S1) AND ((A(3) XOR (not B(3))) XOR Cout2)) OR ((S0) AND (S1) AND (((not A(3)) XOR B(3)) XOR Cout2)));
Cout <=(((not S0) AND (not S1) AND ((A(3) AND const) OR ((A(3) XOR const)AND Cout2))) OR ((S0) AND (not S1) AND ((A(3) AND B(3)) OR ((A(3) XOR B(3))AND Cout2)))) OR (((not S0) AND (S1) AND ((A(3) AND (not B(3))) OR ((A(3) XOR (not B(3)))AND Cout2))) OR ((S0) AND (S1) AND (((not A(3)) AND B(3)) OR (((not A(3)) XOR B(3))AND Cout2))));
F(0) <=((not M) AND LOGout(0)) OR (M AND ARToutF(0));
F(1) <=((not M) AND LOGout(1)) OR (M AND ARToutF(1));
F(2) <=((not M) AND LOGout(2)) OR (M AND ARToutF(2));
F(3) <=((not M) AND LOGout(3)) OR (M AND ARToutF(3));
signbit <= ARToutF(3);
process(ARToutF)
begin
case ARToutF is
when “0000” => SevenSegment <= “0000001”; — “0”
when “0001” => SevenSegment <= “1001111”; — “1”
when “0010” => SevenSegment <= “0010010”; — “2”
when “0011” => SevenSegment <= “0000110”; — “3”
when “0100” => SevenSegment <= “1001100”; — “4”
when “0101” => SevenSegment <= “0100100”; — “5”
when “0110” => SevenSegment <= “0100000”; — “6”
when “0111” => SevenSegment <= “0001101”; — “7”
when “1000” => SevenSegment <= “0000000”; — “8”
when “1001” => SevenSegment <= “0001101”; — “9”
when “1010” => SevenSegment <= “0100000”; — a
when “1011” => SevenSegment <= “0100100”; — b
when “1100” => SevenSegment <= “1001100”; — C
when “1101” => SevenSegment <= “0000110”; — d
when “1110” => SevenSegment <= “0010010”; — E
when “1111” => SevenSegment <= “1001111”; — F
when others => SevenSegment <= “1111111”; — F
end case;
end process;
end Behavioral;
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Pins
I defined the pins in bellow code.
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NET “A(0)” LOC = “P15”;
NET “A(1)” LOC = “P12”;
NET “A(2)” LOC = “P5”;
NET “A(3)” LOC = “P4”;
NET “B(0)” LOC = “P94”;
NET “B(1)” LOC = “P90”;
NET “B(2)” LOC = “P88”;
NET “B(3)” LOC = “P85”;
NET “M” LOC = “P34”;
NET “Cin” LOC = “P35”;
NET “S1” LOC = “P78”;
NET “S0” LOC = “P82”;
NET “Cout” LOC = “P77”;
NET “Signbit” LOC = “P83”;
NET “F(0)” LOC = “P16”;
NET “F(1)” LOC = “P13”;
NET “F(2)” LOC = “P6”;
NET “F(3)” LOC = “P3”;
NET “SevenSegment<0>” LOC = “P64” ;
NET “SevenSegment<1>” LOC = “P98” ;
NET “SevenSegment<2>” LOC = “P73” ;
NET “SevenSegment<3>” LOC = “P72” ;
NET “SevenSegment<4>” LOC = “P65” ;
NET “SevenSegment<5>” LOC = “P62” ;
NET “SevenSegment<6>” LOC = “P71” ;
kod bu haliyle çalışmadı koda uygun olduğunu düşündüğüm bir sim. code yazdım ancak simulasyon çalışmadı similasyon kodu elinizde varsa paylaşabilir misiniz
projem için koda ihtiyacım var kodun ıse design vhdl ve sim doyaları varsa mailime gönderebilir misiniz şimdiden çok teşekkür ederim
Bu projeyi çok eskiden yapmıştım şuan elimde proje dosyaları yok.