Table of Contents
Introduction
Aim of this lab activities is implementing XOR gate in VHDL on FPGA (Xilinx Spartan 3A) board with using Xilinx Design Tools program and upload code using Prometheus software packages.
Methodology
Design
In this lab I try to implement XOR gate at Figure 2.1.1. So that we use the 2 NOT gate 2 AND gate and 1 OR gate for implement XOR gate. Firstly, X and Y are inputs are our gate and Z is output. If we implement figure step by step, not X and Y are inputs of the first AND gate and X and not Y are other of the AND gate’s inputs then these AND gates’ Figure 2.1.1
outputs are the inputs of the OR gate.
Code
VHDL code
In the Lab1Code.vhd file at the Appendix 6.1. shows our implementation code for the XOR gate. Firstly, I identified inputs and outputs these are; X and Y are inputs and Z is outputs. After that, I identified new signals these are; NY (not Y), NX (not X), NXY (not X AND Y) and XNY (X AND not Y). After that I wrote the code for implements these new signals. NX equals not X, NY equals not Y NXY equals not X AND Y XNY equals X AND not Y then Z equals NXY OR XNY.
UCF pins
In the Lab1Pins.ucf file at the Appendix 6.2. shows our implementation code for the boards input and outputs. These are; X equals the P15 switch, Y equals P12 switch and Z equals the P13 led
VHDL simulation
In the mysimulation.vhd file at the Appendix 6.3. shows our implementation code for the simulation. In the simulation code I tested all probabilities these are; x = 0 Y = 0, X = 1 Y = 0,
X = 0 Y = 1, X = 1 Y = 1 and I give the inputs these variable and I initialize the units under test for the all ports (X, Y and Z). You can see the result at 3.1. Simulation.
Results
Simulation
You can see the simulation result on the Figure 3.1.1. 
Figure 3.1.1.
At the simulation result shows that;
If X = 0 and Y = 0, Z = 0
If X = 0 and Y = 1, Z = 1
If X = 1 and Y = 0, Z = 1
If X = 1 and Y = 1, Z = 0
Board
If X = 0 and Y = 0, Z = 0 If X = 0 and Y = 1, Z = 1 If X = 1 and Y = 0, Z = 1 If X = 1 and Y = 1, Z = 0
Discussion
Problems
In the lab I encounter some problems. These are the computer problems on the class. In my first program can not run the simulation so that, I change the computer than the problems solved. Another problem the Libraries, I don’t understand the using libraries because I don’t know the which libraries must using for which syntax. In this lab this is not problem but If other labs will be using different libraries maybe I can not the know the which libraries must be used.
Linux Ubuntu
I have the virtual box program which is the prepare the virtual machine. I setup the Linux Ubuntu on my computer but I can not the setup Xilinx. If the TA send the tutorial about the Linux Ubuntu I will be glad to this.
Conclusion
In this Lab, I learnt the VHDL coding and simulation the code also uploads the using Prometheus. This lab is more like the tutorial about Spartans and Xilinx. I believe next assignments have more difficulties and more implements.
Appendix
Lab1Code.vhl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;
— Uncomment the following library declaration if instantiating
— any Xilinx primitives in this code.
–library UNISIM;
–use UNISIM.VComponents.all;
entity Lab1Code is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC);
end Lab1Code;
architecture Behavioral of Lab1Code is
signal NX : STD_LOGIC;
signal NY : STD_LOGIC;
signal NXY : STD_LOGIC;
signal XNY : STD_LOGIC;
begin
NX <= not X;
NY <= not Y;
NXY <= NX and Y;
XNY <= X and NY;
Z <= NXY or XNY;
end Behavioral;
Lab1Pins.ucf
NET “X” LOC = “P15”;
NET “Y” LOC = “P12”;
NET “Z” LOC = “P13”;
mysimulation.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–USE ieee.numeric_std.ALL;
ENTITY mysimulation IS
END mysimulation;
ARCHITECTURE behavior OF mysimulation IS
— Component Declaration for the Unit Under Test (UUT)
COMPONENT Lab1Code
PORT(
X : IN std_logic;
Y : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
–Inputs
signal X : std_logic := ‘0’;
signal Y : std_logic := ‘0’;
–Outputs
signal Z : std_logic;
— No clocks detected in port list. Replace clock below with
— appropriate port name
constant clock_period : time := 10 ns;
BEGIN
— Instantiate the Unit Under Test (UUT)
uut: Lab1Code PORT MAP (
X => X,
Y => Y,
Z => Z
);
— Clock process definitions
— Stimulus process
stim_proc: process — Stimulus process
begin
X <= ‘0’; Y <= ‘0’;
wait for Clock_period;
X <= ‘1’; Y <= ‘0’;
wait for Clock_period;
X <= ‘0’; Y <= ‘1’;
wait for Clock_period;
X <= ‘1’; Y <= ‘1’;
wait for Clock_period;
X <= ‘0’; Y <= ‘0’; — Return to initial value
wait;
end process;
— insert stimulus here
END;